Clock-Level Trace

Clock-Level Trace

The trace display was taken from an EA 486 emulator. The trace frames are collected on each clock cycle, so the resolution is much higher than trace collected on bus cycles. Each bus cycle consists of two or more clock cycles.

-1430
The trace shows frames -1430 through -1408. The frame numbers count down to zero as you near the end of the trace buffer.

timestamp
-42.920 us
The next column shown is the timestamp, which shows frame -1430 is 42.92 microseconds from frame 0, and frame -1408 is 42.24 microseconds from frame 0. The resolution of the timestamp is 40 ns.

address
00002020
The next column shows the address. Since the resolution is clock cycle, you will see the same address over a series of trace frames that form a single bus cycle.

bbbb
data eeee

3210
500003B8 0000
The next column shows the data. This field must be used in conjunction with the next column, which shows the byte enable signals. There are four byte enable signals, which determine which of the four bytes of the data bus are active. If the byte enable is 0, then it is "enabled" and will read the appropriate byte. In the first clock frames the byte enables are all 0, so during these cycles all four bytes of the bus are being read. frames -1430 and -1429 show a memory code read bus cycle that takes two clocks. This is followed by another two-clock memory code read.

mdw
icr
o
MCR
The next column shows the cycle type. The first of the three columns can be either M for memory, or I for I/O. The second column can be either C for code or D for data. The third column can be either R for read or W for Write. MCR is a Memory Code Read, and ICW is an I/O Code Write.

rb
dr
yy
01
The next two columns show the state of the ready and the bready signals. The 0 indicates active, so frame -1430 shows ready is the active signal.

bbsk
s1me
86an
1110
The next group of four signals control or give status on various functions of the chip. The first, bs8 (when active low), causes the processor to operate on an 8-bit bus. This is seen during startup when the target is reading from 8-bit ROM parts. The next signal, b16 (when enabled), causes the processor to operate on a 16-bit bus. This may be used by certain ROM parts during bootup. Some boards may be implemented with 16-bit buses. Next is the sma, or system management active, which lets you know the processor has entered system management mode. The final signal in the group is the ken or cache enable signal. This is active low, so the cache is enabled during this trace.